An in-memory computing multiply-and-accumulate circuit based on ternary STT-MRAMs for convolutional neural networks

IEICE Electronics Express

article

Guihua Zhao¹  Xing Jin¹  Huafeng Ye²  Yating Peng²  Wei Liu¹  Ningyuan Yin²  Weichong Chen²  Jianjun Chen¹  Ximing Li¹  Zhiyi Yu² 

[1] School of Electronics and Information Technology, Sun Yat-sen University;School of Microelectronics Science and Technology, Sun Yat-sen University;Guangdong Provincial Key Laboratory of Optoelectronic Information Processing Chips and Systems, Sun Yat-Sen University

关键词: in-memory computing;    STT-MRAM;    multiply-and-accumulate;    ternary neural networks;    binary neural networks;   

DOI  :  10.1587/elex.19.20220399

学科分类：电子、光学、磁材料

来源: Denshi Jouhou Tsuushin Gakkai

【 摘 要 】

In-memory computing (IMC) quantized neural network (QNN) accelerators are extensively used to improve energy-efficiency. However, ternary neural network (TNN) accelerators with bitwise operations in nonvolatile memory are lacked. In addition, specific accelerators are generally used for a single algorithm with limited applications. In this report, a multiply-and-accumulate (MAC) circuit based on ternary spin-torque transfer magnetic random access memory (STT-MRAM) is proposed, which allows writing, reading, and multiplying operations in memory and accumulations near memory. The design is a promising scheme to implement hybrid binary and ternary neural network accelerators.

【 授权许可】

CC BY