Low jitter design for quarter-rate CDR of 100Gb/s PAM4 optical receiver

IEICE Electronics Express

article

Sheng Xie¹  Chengkui Jia¹  Luhong Mao²  Gaolei Zhou²  Naibo Zhang³  Ruiliang Song³ 

[1] Tianjin Key Laboratory of Imaging and Sensing Micro-electronic Technology, School of Microelectronics, Tianjin University;School of Electrical and Information Engineering, Tianjin University;The 54th Research Institute, China Electronics Technology Group Corporation

关键词: PAM4;    CDR;    low jitter;    high-speed optical receiver;    SiGe BiCMOS;   

DOI  :  10.1587/elex.19.20220281

学科分类：电子、光学、磁材料

来源: Denshi Jouhou Tsuushin Gakkai

【 摘 要 】

In the ultra-high speed four-level pulse amplitude modulation (PAM4) optical receiver, the data phase jitter is deteriorated by inter-symbol interference (ISI), level transitions and sampling clock. This paper analyzed in detail the causes of phase jitter, and then proposed a novel PAM4 clock and data recovery (CDR) architecture. A three-lane quarter-rate phase detector with majority voter was employed to suppress the input phase jitter caused by discrete zero-crossings, and an optimized quadrature voltage-controlled oscillator (QVCO) was designed to provide stable and precise sampling clock. The PAM4 CDR was optimally designed based on IHP 0.13µm SiGe BiCMOS process, and the post-simulation results indicates that our CDR can operate properly at 100Gb/s with a peak-to-peak jitter of 5.52ps.

【 授权许可】

CC BY