A low-jitter BMCDR for half-rate PON systems

IEICE Electronics Express

Jae-Hun Jung¹  Dong-Hyun Yoon²  Yohan Hong²  Youngkwon Jo²  Kwang-Hyun Baek² 

[1] Device Solution Division, Samsung Electronics;School of Electrical and Electronics Engineering, Chung-Ang University

关键词: burst-mode clock and data recovery;    gated voltage controlled oscillator;    low jitter;    half-rate;    digital frequency calibration;   

DOI  :  10.1587/elex.13.20161045

学科分类：电子、光学、磁材料

来源: Denshi Jouhou Tsuushin Gakkai

【 摘 要 】

This letter presents a 2.5 Gb/s half-rate burst-mode clock and data recovery (BMCDR) with enhanced jitter performance. Compared to conventional half-rate BMCDRs, the proposed work uses a single loop gated voltage controlled oscillator (GVCO) to minimize the timing mismatch. And the GVCO has only one gated delay cell to improve jitter performances. In addition, a tri-state phase detector for digital frequency calibration is also proposed in this letter to further reduce jitter caused by the frequency offset between the input data and the GVCO free running clock. The fabricated chip in a 110 nm CMOS technology occupies the area of 0.08 mm2. The proposed BMCDR consumes 29 mW with the measured peak to peak jitter of 17.8 psp–p (0.022 UIp–p).

【 授权许可】

CC BY