Techniques for SAT-Based Boolean Reasoning on Multiple Faults Affecting Logic Cells and Interconnects in Digital ICs

Electronics

Michele Favalli¹  Francesco Dall’Occo¹  Marcello Dalpasso² 

[1] Department of Engineering, University of Ferrara, Viale Saragat, 2, 44122 Ferrara, Italy;Department of Information Engineering, University of Padova, Viale Gradenigo, 6A, 35131 Padova, Italy;

关键词: digital integrated circuits;    multiple faults;    fault diagnosis;    reliability analysis;    Boolean satisfiability;   

DOI  :  10.3390/electronics11030382

来源: DOAJ

【 摘 要 】

We propose a new method for SAT-based Boolean reasoning on multiple defects in digital ICs. Although it does not explicitly consider a specific fault model such as model-based techniques, it allows us to consider more realistic cases than model-free approaches. In particular, it can be used to account for (a) faults resulting in monotonic errors at the output of a cell and (b) faults, such as breaks or bridgings, that may corrupt the propagation of a signal from its fan-out branches. The model can be used for either standard gates or more complex combinational modules. Examples are shown for applications requiring the consideration of multiple defects such as fault diagnosis and reliability analysis. The feasibility of the proposed approach is assessed by results on a set of combinational benchmarks.

【 授权许可】

Unknown