Optimal Physical Implementation of Radiation Tolerant High-Speed Digital Integrated Circuits in Deep-Submicron Technologies

Electronics

Karel Appels¹  Jeffrey Prinzie¹  Szymon Kulis² 

[1] Deptartment of Electrical Engineering (ESAT), KU Leuven, 3000 Leuven, Belgium;European Center for Nuclear Research (CERN), 1211 Meyrin, Switzerland;

关键词: single-event upsets (SEUs);    digital integrated circuits;    triple modular redundancy (TMR);    radiation hardening by design;   

DOI  :  10.3390/electronics8040432

来源: DOAJ

【 摘 要 】

This paper presents a novel scalable physical implementation method for high-speed Triple Modular Redundant (TMR) digital integrated circuits in radiation-hard designs. The implementation uses a distributed placement strategy compared to a commonly used bulk 3-bank constraining method. TMR netlist information is used to optimally constrain the placement of both sequential cells and combinational cells. This approach significantly reduces routing complexity, net lengths and dynamic power consumption with more than 60% and 20% respectively. The technique was simulated in a 65 nm Complementary Metal-Oxide Semiconductor (CMOS) technology.

【 授权许可】

Unknown