High-Performance Time Server Core for FPGA System-on-Chip

Electronics

Paulino Ruiz-de-Clavijo¹  Enrique Ostua¹  Manuel J. Bellido¹  David Guerrero¹  German Cano¹  Jorge Juan-Chico¹  Julian Viejo¹ 

[1] Electronics Technology Department, E.T.S. Ingeniería Informática, University of Seville, Avda. Reina Mercedes s/n, 41012 Seville, Spain;

关键词: system-on-chip;    digital integrated circuits;    field programmable gate array;    network time synchronization;    network time protocol;    hardware timestamping;    Internet of Things;   

DOI  :  10.3390/electronics8050528

来源: DOAJ

【 摘 要 】

This paper presents the complete design and implementation of a low-cost, low-footprint, network time protocol server core for field programmable gate arrays. The core uses a carefully designed modular architecture, which is fully implemented in hardware using digital circuits and systems. Most remarkable novelties introduced are a hardware-optimized timekeeping algorithm implementation, and a full-hardware protocol stack and automatic network configuration. As a result, the core is able to achieve similar accuracy and performance to typical high-performance network time protocol server equipment. The core uses a standard global positioning system receiver as time reference, has a small footprint and can easily fit in a low-range field-programmable chip, greatly scaling down from previous system-on-chip time synchronization systems. Accuracy and performance results show that the core can serve hundreds of thousands of network time clients with negligible accuracy degradation, in contrast to state-of-the-art high-performance time server equipment. Therefore, this core provides a valuable time server solution for a wide range of emerging embedded and distributed network applications such as the Internet of Things and the smart grid, at a fraction of the cost and footprint of current discrete and embedded solutions.

【 授权许可】

Unknown