A Zero-Cost Technique to Improve ON-State Performance and Reliability of Power LDMOS Transistors

IEEE Journal of the Electron Devices Society

Nihar R. Mohapatra¹  Kumari Neeraj Kaushal¹ 

[1] Department of Electrical Engineering, Indian Institute of Technology Gandhinagar, Gandhinagar, India;

关键词: PMIC;    LDMOS;    doping gradient;    breakdown voltage;    specific on-resistance;    trans-conductance;   

DOI  :  10.1109/JEDS.2021.3059854

来源: DOAJ

【 摘 要 】

In this paper, we have proposed a simple and zero-cost technique to improve ON-state and reliability performance of LDMOS transistors. We introduced doping gradient in the channel by optimizing position of the P-Well mask during test structure design/layout. Through proper device design, fabrication and measurement on different test structures, we have shown that the graded channel significantly improves the drive capability (upto ~30%), analog FoMs and hot-carrier reliability of LDMOS transistors without any penalty on the OFF-state performance. The performance improvement is independent of drift region design (breakdown voltage). The device physics behind different observations is also discussed with detailed TCAD simulations.

【 授权许可】

Unknown