Evaluating the Impact of Optical Interconnects on a Multi-Chip Machine-Learning Architecture

Electronics

Yuhwan Ro¹  Eojin Lee¹  JungHo Ahn¹ 

[1] Department of Transdisciplinary Studies, Seoul National University, Seoul 08826, Korea;

关键词: machine learning;    accelerator;    optical interconnect;    multi-chip architecture;    cluster;    Convolutional Neural Network (CNN);   

DOI  :  10.3390/electronics7080130

来源: DOAJ

【 摘 要 】

Following trends that emphasize neural networks for machine learning, many studies regarding computing systems have focused on accelerating deep neural networks. These studies often propose utilizing the accelerator specialized in a neural network and the cluster architecture composed of interconnected accelerator chips. We observed that inter-accelerator communication within a cluster has a significant impact on the training time of the neural network. In this paper, we show the advantages of optical interconnects for multi-chip machine-learning architecture by demonstrating performance improvements through replacing electrical interconnects with optical ones in an existing multi-chip system. We propose to use highly practical optical interconnect implementation and devise an arithmetic performance model to fairly assess the impact of optical interconnects on a machine-learning accelerator platform. In our evaluation of nine Convolutional Neural Networks with various input sizes, 100 and 400 Gbps optical interconnects reduce the training time by an average of 20.6% and 35.6%, respectively, compared to the baseline system with 25.6 Gbps electrical ones.

【 授权许可】

Unknown