Flat vapor chamber technology is well-studied. The technology effectively spreads heat from a source, like an integrated circuit (IC) package, over a larger heat sink area. This technology has been commercially utilized and can provide significant improvement in reducing hot spot temperatures for non-uniformly powered chips. Recent studies have also applied this technology to lower thermal spreading resistance of a shared heat sink for multi-chip modules to cool multiple components on the same substrate [1]. However, these studies have focused on relatively small footprint areas (e.g. 60 mm x 60 mm [2]). Also, they have focused mainly on steady state operating conditions, with a few recent studies starting to examine the effect of a time variant power map on vapor chamber performance [3]. In this work, we consider a much larger circuit board/substrate with many IC packages with time variant total board power and power map. The present work uses power maps to emulate the thermal response of computer architecture design of high bandwidth memory packages where the memory packages act as local or embedded memory for microprocessors. We present a case of two 100W microprocessors surrounded by 64 GB memory packages of 10W each. We explore the limitations of a vapor chamber of large footprint area (110 mm x 110 mm) in cooling a dynamically changing power map. We present a simplified model to represent flow in a porous media. The model uses potential flow theory to reduce the complexity present, due to Darcy flow, in porous media. The parameter of the simplified model is tuned to match a computational fluid dynamics model for steady state cases. The model is then used to study capillarity limitation of the large vapor chamber in delivering liquid flow to heat source locations for steady state. The model is then extended to study transient liquid flow patterns resulting from a change in the power map of the multiple heat sources.
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