Performance Investigation of Single Grain Boundary Junctionless Field Effect Transistor

IEEE Journal of the Electron Devices Society

Dawit Burusie Abdi¹  Mamidala Saketh Ram² 

[1] Department of Electrical Engineering, Indian Institute of Technology, New Delhi, India;Faculty of Electrical Engineering and Information Technology, TU Chemnitz, Chemnitz, Germany;

关键词: Junctionless FET (JLFET);    thin-film transistor (TFT);    poly-Si;    grain boundary (GB);    simulation;    glass substrates;   

DOI  :  10.1109/JEDS.2016.2600375

来源: DOAJ

【 摘 要 】

In this paper, we report a single grain boundary (GB) junctionless thin film transistor (JLFET) on recrystallized polycrystalline silicon (poly-Si JLFET). Using 2-D simulations, the electrical performance of the poly-Si JLFET is evaluated for different single GB locations in the channel. Without the need for creating the source and the drain regions by implantation, we demonstrate the prospect of achieving thin-film poly-Si JLFETs whose performance is reasonable for silicon film thicknesses less than 10 nm.

【 授权许可】

Unknown