Sub-10 nm Scalability of Junctionless FETs Using a Ground Plane in High-K BOX: A Simulation Study

IEEE Access

卷:8

Mamidala Jagadesh Kumar¹  Aakash Kumar Jain² 

[1] Indian Institute of Technology Delhi, New Delhi, India;

[2] National University of Singapore, Singapore;

关键词: Band-to-band tunneling (BTBT);    gate induced drain leakage (GIDL);    Junctionless FET (JLFET);    parasitic bipolar junction transistor (BJT);    drain induced barrier lowering (DIBL);   

DOI  :  10.1109/ACCESS.2020.3012579

来源: DOAJ

【 摘 要 】

The leakage mechanisms of inefficient volume depletion and lateral band to band tunneling (L-BTBT) restrict the scaling of SOI-junctionless (JL) FETs. Therefore, in this article, we investigate the scalability of the SOI-JLFETs by incorporating a ground plane (GP) inside a high-K buried oxide (BOX). Using calibrated 2-D simulations, it is demonstrated that a SOI-JLFET with the ground plane placed at a shallow depth within the high-K dielectric BOX not only assists in the efficient volume depletion of the channel but also results in a drastically reduced L-BTBT action. The efficient volume depletion, therefore, relaxes the constraints of ultra-thin silicon body for SOI-JLFET and circumvents the need of complex device architectures for achieving the same. Also, the depletion of the drain and source regions jointly results in a drastically reduced L-BTBT induced parasitic BJT action in the OFF-state and in the negative bias regime. The simultaneous suppression of both the leakage mechanisms results in an overall leakage current reduction leading to a significant ON-state to OFF-state current ratio (ION/IOFF) of 106 and 105 even at the scaled gate length of 10 nm and 7 nm, respectively. Additionally, a significant reduction in the drain-induced barrier lowering and threshold voltage roll-off is observed in a GP-JLFET. The GP-JLFET also exhibits an appreciable ION/IOFF ratio under the influence of process variations of doping and film thickness without any considerable degradation in the performance. Thus, the suppressed leakage mechanisms and short channel effects in the proposed device provide an incentive for realizing the SOI-JLFETs in the sub-10 nm regime for low power and low-leakage applications.

【 授权许可】

Unknown