Resource- and Power-Efficient High-Performance Object Detection Inference Acceleration Using FPGA

Electronics

Solomon Negussie Tesema¹  El-Bay Bourennane¹ 

[1] Laboratory ImViA, University of Burgundy, 21000 Dijon, France;

关键词: hardware acceleration;    object detection;    FPGA;    deep learning;    YOLOv2;    CNN;   

DOI  :  10.3390/electronics11121827

来源: DOAJ

【 摘 要 】

The success of deep convolutional neural networks in solving age-old computer vision challenges, particularly object detection, came with high requirements in terms of computation capability, energy consumption, and a lack of real-time processing capability. However, FPGA-based inference accelerations have recently been receiving more attention from academia and industry due to their high energy efficiency and flexible programmability. This paper presents resource-efficient yet high-performance object detection inference acceleration with detailed implementation and design choices. We tested our object detection acceleration by implementing YOLOv2 on two FPGA boards and achieved up to 184 GOPS with limited resource utilization.

【 授权许可】

Unknown