Hardware accelerated search for resource-efficient and secure permutation matrices

IEICE Electronics Express

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[1] Computer Engineering Dept, Food and Agriculture University

关键词: hardware acceleration;    FPGA;    symmetric cryptography;    block cipher;    permutation layer;   

DOI  :  10.1587/elex.13.20160352

学科分类：电子、光学、磁材料

来源: Denshi Jouhou Tsuushin Gakkai

【 摘 要 】

References(12)Permutation layer is a core component of substitution-permutation network block ciphers. Its design directly affects security and resource usage of the block cipher. It is a challenging problem to find permutation matrices with respect to predefined trade-off targets. In our work, we developed a hardware search engine on Xilinx Virtex-6 FPGA in order to accelerate the search of resource-efficient and secure (maximal branch number) 16 × 16 permutation matrices. Our engine completed the full spectrum search in 129 hours 48 minutes and found non-involutory and involutory permutation matrices with maximal branch number of 5 and minimum Hamming weight (HW) of 74 and 80, respectively. To the best of our knowledge, this is the first time that such a hardware accelerated custom search engine has been built and full spectrum permutation matrix search has been performed.

【 授权许可】

Unknown