Characterization and Compact Modeling of Nanometer CMOS Transistors at Deep-Cryogenic Temperatures

IEEE Journal of the Electron Devices Society

Lin Song¹  Andrei Vladimirescu²  Harald Homulle³  Rosario M. Incandela³  Fabio Sebastiano³  Edoardo Charbon⁴ 

[1] Analog Devices, Inc., Beijing, China;Berkeley Wireless Research Center, University of California at Berkeley, Berkeley, CA, USA;Department of Quantum and Computer Engineering, Delft University of Technology, Delft, The Netherlands;Kavli Institute of Nanoscience, Delft, The Netherlands;

关键词: Cryogenic electronics;    CMOS;    cryogenic;    cryo-CMOS;    characterization;    modeling;   

DOI  :  10.1109/JEDS.2018.2821763

来源: DOAJ

【 摘 要 】

Cryogenic characterization and modeling of two nanometer bulk CMOS technologies (0.16-μm and 40-nm) are presented in this paper. Several devices from both technologies were extensively characterized at temperatures of 4 K and below. Based on a detailed understanding of the device physics at deep-cryogenic temperatures, a compact model based on MOS11 and PSP was developed. In addition to reproducing the device dc characteristics, the accuracy and validity of the compact models are demonstrated by comparing time- and frequency-domain simulations of complex circuits, such as a ring oscillator and a low-noise amplifier, with the measurements at 4 K.

【 授权许可】

Unknown