Low Power Clock Network Design

Journal of Low Power Electronics and Applications

Inna Vaisband²  Eby G. Friedman²  Ran Ginosar¹ 

[1] Department of Electrical Engineering, Technion–Israel Institute of Technology, Haifa 32000, Israel; E-Mails:;Department of Electrical and Computer Engineering, University of Rochester, Rochester, NY 14627, USA; E-Mail:

关键词: low power;    skew;    skew variation;    crosslinks;    mesh;    topologies;   

DOI  :  10.3390/jlpea1010219

来源: mdpi

【 摘 要 】

Power is a primary concern in modern circuits. Clock distribution networks, in particular, are an essential element of a synchronous digital circuit and a significant power consumer. Clock distribution networks are subject to clock skew due to process, voltage, and temperature (PVT) variations and load imbalances. A target skew between sequentially-adjacent registers can be obtained in a balanced low power clock tree using techniques such as buffer and wire sizing. Existing skew mitigation techniques in tree-based clock distribution networks, however, are not efficient in coping with post design variations; whereas the latest non-tree mesh-based solutions reliably handle skew variations, albeit with a significant increase in dissipated power. Alternatively, crosslink-based methods provide low power and variation-efficient skew solutions. Existing crosslink-based methods, however, only address skew at the network topology level and do not target low power consumption. Different methods to manage skew and skew variations within tree and non-tree clock distribution networks are reviewed and compared in this paper. Guidelines for inserting crosslinks within a buffered low power clock tree are provided. Metrics to determine the most power efficient technique for a given circuit are discussed and verified with simulation.

【 授权许可】

CC BY   
© 2011 by the authors; licensee MDPI, Basel, Switzerland.