Design and implementation of clock network for nanometer FPGA

IEICE Electronics Express

Lei Li¹  Jinmei Lai¹ 

[1] ASIC and System State Key Lab, Dept. of Microelectronics, FudanUniversity

关键词: clock network;    FPGA;    skew;    latency;    DAU;   

DOI  :  10.1587/elex.12.20141180

学科分类：电子、光学、磁材料

来源: Denshi Jouhou Tsuushin Gakkai

【 摘 要 】

References(17)This paper is committed to design and implement FPGA clock network with overall considerations of speed and power in circuit design perspective. Mixed structure MUX, programmable delay adjustment unit and power-down bit strategies are presented to optimize its latency, skew and power. This clock network is implemented with 65 nm process and applied to own-designed FPGA. Test results indicate 21.7% reduction in latency and 54.5% reduction in skew, compared to counterpart FPGA device, while maintaining lower power consumption.

【 授权许可】

Unknown