Exploration of Sub-VT and Near-VT 2T Gain-Cell Memories for Ultra-Low Power Applications under Technology Scaling

Journal of Low Power Electronics and Applications

Pascal Meinerzhagen²  Adam Teman¹  Robert Giterman¹  Andreas Burg² 

[1] VLSI Systems Center, Ben-Gurion University of the Negev, POB 653, Be’er Sheva 84105, Israel; E-Mails:;Institute of Electrical Engineering, Ecole Polytechnique Fédérale de Lausanne, Station 11, Lausanne, VD 1015, Switzerland; E-Mail:

关键词: embedded memory;    gain cell;    energy efficiency;    subthreshold operation;    near-threshold operation;    retention time;    access speed;    technology scaling;   

DOI  :  10.3390/jlpea3020054

来源: mdpi

【 摘 要 】

Ultra-low power applications often require several kb of embedded memory and are typically operated at the lowest possible operating voltage ( operation at the mature node, we find that the scaled 40 nm node requires a near-threshold 600 mV supply to achieve at least 97% read/write availability due to higher leakage currents that limit the bitcell’s retention time. Monte Carlo simulations show that a 600 mV 2 kb 40 nm gain-cell array is fully functional at frequencies higher than 50 MHz.

【 授权许可】

CC BY   
© 2013 by the authors; licensee MDPI, Basel, Switzerland.