CMOS latch bit-cell array for low-power SRAM design

IEICE Electronics Express

Yeonbae Chung¹  Weijie Cheng¹ 

[1] School of Electrical Engineering and Computer Science, Kyungpook National University

关键词: SRAM;    4-transistor cell;    low-power;    embedded memory;   

DOI  :  10.1587/elex.7.1145

学科分类：电子、光学、磁材料

来源: Denshi Jouhou Tsuushin Gakkai

【 摘 要 】

References(2)Cited-By(1)The design and physical implementation of a low-power SRAM with 4T CMOS latch bit-cell is presented. The memory cells in this work are composed of two cross-coupled inverters without any access transistors. They are accessed by totally novel read and write methods that result in low operating power dissipation in the nature. A 1.8V SRAM test chip has been fabricated in a 0.18µm CMOS technology, which demonstrated the functionality of the memory cell. This new SRAM operates with 30% reduction in read power and 42% reduction in write power compared to the standard 6T SRAM.

【 授权许可】

Unknown