The Impact of Process Scaling on Scratchpad Memory Energy Savings †

Journal of Low Power Electronics and Applications

Bennion Redd²  Spencer Kellis³  Nathaniel Gaskin¹ 

[1] 701 E Charleston Rd, Palo Alto, CA 94303, USA; E-Mail:;Department of Electrical & Computer Engineering, University of Utah, 1692 Warnock Engineering Bldg., 72 S. Central Campus Dr., Salt Lake City, UT 84112, USA; E-Mail:;Division of Biology and Biological Engineering, California Institute of Technology, Mail Code 216-76, 1200 E, California Blvd., Pasadena, CA 91125, USA; E-Mail:

关键词: scratchpad memory;    loop cache;    process scaling;    low power;    microprocessor;    computer architecture;    embedded;   

DOI  :  10.3390/jlpea4030231

来源: mdpi

【 摘 要 】

Scratchpad memories have been shown to reduce power consumption, but the different characteristics of nanometer scale processes, such as increased leakage power, motivate an examination of how the benefits of these memories change with process scaling. Process and application characteristics affect the amount of energy saved by a scratchpad memory. Increases in leakage as a percentage of total power particularly impact applications that rarely access memory. This study examines how the benefits of scratchpad memories have changed in newer processes, based on the measured performance of the WIMS (Wireless Integrated MicroSystems) microcontroller implemented in 180- and 65-nm processes and upon simulations of this microcontroller implemented in a 32-nm process. The results demonstrate that scratchpad memories will continue to improve the power dissipation of many applications, given the leakage anticipated in the foreseeable future.

【 授权许可】

CC BY   
© 2014 by the authors; licensee MDPI, Basel, Switzerland.