Hardware-Efficient Delta Sigma-Based Digital Signal Processing Circuits for the Internet-of-Things

Journal of Low Power Electronics and Applications

Yifei Liu²  Paul M. Furth²  Wei Tang¹ 

[1] Klipsch School of Electrical and Computer Engineering, New Mexico State University, 1125 Frenger Mall, Las Cruces, NM 88003, USA;

关键词: VLSI;    Delta Sigma modulation;    digital signal processing;    adder;    coefficient multiplier;    low-power low-complexity circuits;   

DOI  :  10.3390/jlpea5040234

来源: mdpi

【 摘 要 】

This paper presents hardware-efficient Delta Sigma linear processing circuits for the next generation low-power VLSI devices in the Internet-of-things (IoT). We first propose the P-N (positive-negative) pair method to manipulate both the analog value and length of a first-order Delta Sigma bit sequence. We then present a binary counter method. Based on these methods, we develop Delta Sigma domain on-the-fly digital signal-processing circuits: the Delta Sigma sum adder, average adder and coefficient multiplier. The counter-based average adder can work with both first-order and higher-order Delta Sigma modulators and can also be used as a coefficient multiplier. The functionalities of the proposed circuits are verified by MATLAB simulation and FPGA implementation. We also compare the area and power between the proposed Delta Sigma adders and a conventional multi-bit adder by synthesizing both circuits in the IBM 0.18-μm technology. Synthesis results show that the proposed Delta Sigma processing circuits can extensively reduce circuit area and power. With 100 inputs, a Delta Sigma average adder saves 94% of the silicon area and 96% of the power compared to a multi-bit binary adder. The proposed circuits have the potential to be widely used in future IoT circuits.

【 授权许可】

CC BY   
© 2015 by the authors; licensee MDPI, Basel, Switzerland.