A Low Power 1024-Channels Spike Detector Using Latch-Based RAM for Real-Time Brain Silicon Interfaces

Electronics

Antonio Giuseppe Maria Strollo¹  Gerardo Saggese¹ 

[1] Department of Electrical Engineering and Information Technology, University of Naples Federico II, 80125 Naples, Italy;

关键词: neuroscience;    brain machine interface;    digital signal processing;    spike detection;    low power;    VLSI;   

DOI  :  10.3390/electronics10243068

来源: DOAJ

【 摘 要 】

High-density microelectrode arrays allow the neuroscientist to study a wider neurons population, however, this causes an increase of communication bandwidth. Given the limited resources available for an implantable silicon interface, an on-fly data reduction is mandatory to stay within the power/area constraints. This can be accomplished by implementing a spike detector aiming at sending only the useful information about spikes. We show that the novel non-linear energy operator called ASO in combination with a simple but robust noise estimate, achieves a good trade-off between performance and consumption. The features of the investigated technique make it a good candidate for implantable BMIs. Our proposal is tested both on synthetic and real datasets providing a good sensibility at low SNR. We also provide a 1024-channels VLSI implementation using a Random-Access Memory composed by latches to reduce as much as possible the power consumptions. The final architecture occupies an area of 2.3 mm², dissipating 3.6 µW per channels. The comparison with the state of art shows that our proposal finds a place among other methods presented in literature, certifying its suitability for BMIs.

【 授权许可】

Unknown