SEU hardened layout design for SRAM cells based on SEU reversal

IEICE Electronics Express

Wei Guo¹  Minxuan Zhang¹  Peng Li¹  Quan Deng¹  Zhenyu Zhao¹ 

[1] College of Computer, National University of Defense Technology

关键词: SRAM cells;    single event upset (SEU);    charge sharing;    single event upset reversal (SEUR);    layout hardened design;   

DOI  :  10.1587/elex.12.20150804

学科分类：电子、光学、磁材料

来源: Denshi Jouhou Tsuushin Gakkai

【 摘 要 】

References(12)Cited-By(2)In this paper, the generation mechanism of single event upset reversal (SEUR) between 2 PMOS in SRAM cells is studied in depth based on 45 nm CMOS technology. We find that SEUR not only depends on the charge sharing but also follows the rule that the charge collection of passive device is larger and longer than that of active device. Based on SEUR generation mechanism, two novel layouts named Drain-Source-Drain (DSD) and Dummy are proposed to increase the rate of SEUR for reducing SEU vulnerability of SRAM cells. Compared with the traditional layout, DSD and Dummy layout reduce 4.26% and 31.56% SEU sensitive area under normal incident, respectively. For tilted incident, Dummy layout sharply increases SEUR rate while DSD layout is not better than the traditional layout on enhancing SEUR. Consequently, the proposed Dummy layout can improve SEU reliability without area penalty.

【 授权许可】

Unknown