Efficient FPGA implementation of sharp FIR filters using the FRM technique

IEICE Electronics Express

Jian Zhang¹  Shuguo Li¹ 

[1] Institute of Microelectronics, Tsinghua University

关键词: frequency response masking technique;    FIR filter;    field programmable gate array;    systolic array;   

DOI  :  10.1587/elex.6.1656

学科分类：电子、光学、磁材料

来源: Denshi Jouhou Tsuushin Gakkai

【 摘 要 】

References(8)Cited-By(1)A high-performance field programmable gate array (FPGA) implementation of full pipelined computation structure is proposed for sharp finite-impulse -response (FIR) filters using the frequency response masking (FRM) technique. The FRM-based FIR (FFIR) filter consists of a novel symmetrical systolic array of a interpolated FIR(IFIR) filter in cascade to a pair of nonsymmetrical systolic arrays of masking FIR filters mainly. These filters are designed based on inner-product computation involving MAC operation which can be realized by the DSP block in the latest FPGA device efficiently. The realization results on a Xilinx Virtex-5 chip show that the proposed FPGA implementation can obtain higher throughput but consumes less resource compared to the equivalent conventional sharp FIR (CSFIR) filter that developed by the Core Generator software tool.

【 授权许可】

Unknown