The design of high holding voltage SCR for whole-chip ESD protection

IEICE Electronics Express

Jong-Ki Kwon¹  Yong-Seo Koo²  Kui-Dong Kim¹  Kwang-Yeob Lee³ 

[1] Electronics and Telecommunications Research Institute;Department of Electronic Engineering Seokyeong University;Department of Computer Engineering Seokyeong University

关键词: ESD;    SCR;    triggering voltage;    holding voltage;   

DOI  :  10.1587/elex.5.624

学科分类：电子、光学、磁材料

来源: Denshi Jouhou Tsuushin Gakkai

【 摘 要 】

References(4)In this paper, we have investigated the electrical characteristics of Silicon Controlled Rectifier (SCR)-based ESD power clamp circuit with high holding voltage for whole-chip ESD protection. The proposed ESD power clamp circuit (HHVSCR: High Holding Voltage SCR) has different well (n/p-well) length (3/7µm - 8/2µm) and p-drift (p+) length (8µm - 16µm). The measurement results indicate that dimension of n/p-well and p-drift has a great effect on holding voltage (2V-5V) and a little effect on the triggering voltage (6.5V∼7V). And the whole-chip ESD protection was designed for 2.5∼3.3V applications, this whole-chip ESD protection design can be discharged in ESD-stress mode (PD, ND, PS, NS) as well as VDD-VSS mode. The robustness of the novel ESD protection cells were measured to 6kV (HBM: Human Body Model), 280V (MM: Machine Model).

【 授权许可】

Unknown