Impact of the double-patterning technique on the LER-induced threshold voltage variation in symmetric tunnel field-effect transistor

IEICE Electronics Express

Changhwan Shin¹  Seulki Park¹  Ju Han Lee¹ 

[1] School of Electrical and Computer Engineering, University of Seoul

关键词: symmetric tunnel field-effect transistor;    CMOS;    random variation;    line-edge roughness (LER);    steep switching;    double patterning;   

DOI  :  10.1587/elex.12.20150349

学科分类：电子、光学、磁材料

来源: Denshi Jouhou Tsuushin Gakkai

【 摘 要 】

References(25)A symmetric tunnel field-effect transistor (S-TFET) was recently proposed as an alternative device to address power density issues, featuring steep switching characteristic and bi-directional current flow with its symmetric structure. Because 193-nm immersion lithography is paired up with double or multiple patterning techniques for further enhancement of patterning resolution, the effect of double-patterning and double-etching (2P2E)-induced gate line-edge roughness (LER) [versus single-patterning and single-etching (1P1E)] on the S-TFET is investigated with various device design parameters. Finally, an investigation is conducted on the physical reasons which give rise to the difference in the LER parameters for 2P2E and 1P1E technique.

【 授权许可】

Unknown