期刊论文详细信息
IEICE Electronics Express | |
A novel design of high-speed divide-by-3/4 counter for a dual-modulus prescaler | |
Yi-Shing Shih1  Jenn-Hwan Tarng1  | |
[1] Department of Communication Engineering, National Chiao Tung University | |
关键词: prescaler; high-speed circuits; synchronous counter; | |
DOI : 10.1587/elex.3.276 | |
学科分类:电子、光学、磁材料 | |
来源: Denshi Jouhou Tsuushin Gakkai | |
【 摘 要 】
References(5)A novel design for a high-speed divide-by-3/4 counter is presented. The proposed design reduces not only the critical path delay but also the feedback path delay, hence it can increase the operating speed. With this divide-by-3/4 counter, a divide-by-127/128 dual-modulus prescaler (DMP), implemented in 0.18µm CMOS technology, shows a maximum operating frequency of 7.0GHz with 2.4mW power consumption at 1.8V supply voltage, which has 25% speed improvement and still consumes less power as well compared to the recently-reported one.
【 授权许可】
Unknown
【 预 览 】
Files | Size | Format | View |
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RO201911300660178ZK.pdf | 314KB | download |