Design of switching-mode CMOS frequency multipliers in sub-Terahertz regime

IEICE Electronics Express

Jung-Dong Park¹ 

[1] Graduate of School of Engineering, University of California

关键词: sub-Terahertz;    CMOS;    multiplier;    tripler;    quadrupler;   

DOI  :  10.1587/elex.11.20140806

学科分类：电子、光学、磁材料

来源: Denshi Jouhou Tsuushin Gakkai

【 摘 要 】

References(6)Switching mode CMOS frequency multipliers are studied in sub-Terahertz regime. Analysis on the multiplier architectures and optimal gate bias at CMOS switch are investigated to maximize output power at designated harmonics. Utilizing a differential pair, a 195 GHz tripler having a hair-pin filter is designed to maximize 3rd harmonics with �?14.8 dB of conversion gain (CG) from Pin = +13 dBm of the balanced input, while the 260 GHz quadrupler utilizes quadruple-push pairs which achieves CG = �?16 dB from two +13 dBm of the balanced I/Q driving signals in a 65 nm digital CMOS process.

【 授权许可】

Unknown