A 0.2 V�?1.8 V 8T SRAM with Bit-interleaving Capability

IEICE Electronics Express

Li Geng¹  Leicheng Chen¹  Hui Zhao¹  Shiquan Fan¹  Yan Song¹ 

[1] School of Electronics and Information Engineering, Xi’an Jiaotong University

关键词: ultra-dynamic voltage scaling (U-DVS);    subthreshold SRAM;    8T cell;    bit-interleaving;   

DOI  :  10.1587/elex.11.20140229

学科分类：电子、光学、磁材料

来源: Denshi Jouhou Tsuushin Gakkai

【 摘 要 】

References(12)Cited-By(1)An 8T SRAM with bit-interleaving capability is designed for ultra-dynamic voltage scaling applications. An adaptive body-biasing scheme is designed to improve the stability of 8T cell, which achieves 1.5 times higher noise margin compared to the non-body-biased 8T cell. Also, a write driver is presented to enable the bit-interleaving structure, thus achieving high soft-error tolerance. A prototype 1-kb SRAM is fabricated in a standard 0.18 µm CMOS process. The measurement results show that the proposed design fulfils the functionality under supply voltage from 1.8 V to 0.3 V (0.2 V when the write wordline is boosted to 0.36 V) and the total power is reduced by four times of magnitude.

【 授权许可】

Unknown