A PMOS read-port 8T SRAM cell with optimized leakage power and enhanced performance

IEICE Electronics Express

Chengying Chen¹  Jia Yuan¹  Jiangzheng Cai²  Yong Hei²  Liming Chen² 

[1] D Centre, Institute of Microelectronics of Chinese Academy of Sciences;Smart Sensing R&

关键词: SRAM;    8T cell;    leakage power;    low power;   

DOI  :  10.1587/elex.14.20161188

学科分类：电子、光学、磁材料

来源: Denshi Jouhou Tsuushin Gakkai

【 摘 要 】

This paper presents a novel PMOS read-port 8T SRAM cell, in which the read circuit is constructed by two cascaded PMOS transistors, and hence the leakage power is significantly optimized compared to the conventional 8T cell. Meanwhile, it also exhibits high area efficiency due to an equalized quantity of NMOS and PMOS transistors per cell. Furthermore, the proposed cell has sufficient potential to enhance performance by employing a Half-Schmitt inverter. The measurements indicate that the proposed cell outmatches conventional 8T cell in terms of leakage suppression and area saving, thus making it a superior choice for ultra low power applications.

【 授权许可】

CC BY