IEICE Electronics Express | |
Metro-on-chip: an efficient physical design technique for congestion reduction | |
Ali Jahanian1  Morteza Saheb Zamani1  | |
[1] Computer Engineering and IT Department, Amirkabir University of Technology | |
关键词: asynchronous serial transmission; congestion; physical design; | |
DOI : 10.1587/elex.4.510 | |
学科分类:电子、光学、磁材料 | |
来源: Denshi Jouhou Tsuushin Gakkai | |
【 摘 要 】
References(7)Cited-By(1)Routing congestion is one of the main factors in designing in deep submicron technology that may cause unroutability of the design, signal integrity problems and large delays in detoured wires. In this paper, a new methodology is presented which multiplexes regular nets by asynchronous serial transceivers in the physical design flow in order to improve the congestion of the design. Experimental results show that for the attempted benchmarks, the overflow congestion was reduced by up to 40.03% without any degradation in clock frequency and negligible power consumption overhead.
【 授权许可】
Unknown
【 预 览 】
Files | Size | Format | View |
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RO201911300433131ZK.pdf | 147KB | download |