TimFastPlace: Critical-path based timing driven FastPlace

IEICE Electronics Express

Kang Zhao²  Jiliang Zhang²  Yaping Lin¹  Qiang Zhou²  Qiang Wu¹  Yongqiang Lu² 

[1] College of Information Science and Engineering, Hunan University;Department of Computer Science and Technology, Tsinghua University

关键词: physical design;    critical path;    static timing analysis;   

DOI  :  10.1587/elex.9.1310

学科分类：电子、光学、磁材料

来源: Denshi Jouhou Tsuushin Gakkai

【 摘 要 】

References(7)In this paper, we propose a critical-path based timing driven FastPlace, named TimFastPlace, which uses an iterative critical path-based weighting model to optimize the critical path delay at the equation solving stage. Experimental results on several industry cases and ISCAS89 cases show that we are able to obtain up to 30.83% Worst Negative Slack (WNS), an average of 23.42% WNS and 18.87% Total Negative Slack (TNS) improvement in circuit delays at an average of 2.54% wire length increase. Besides, runtime is kept at the same level as FastPlace.

【 授权许可】

Unknown