Minimizing the adder cost in multiple constant multipliers

IEICE Electronics Express

S. Rahimian Omam¹  O. Shoaei¹  S. M. Fakhraie¹ 

[1] IC Design Center, University of Tehran

关键词: digital filter;    adder cost;    graph representation;   

DOI  :  10.1587/elex.3.340

学科分类：电子、光学、磁材料

来源: Denshi Jouhou Tsuushin Gakkai

【 摘 要 】

References(4)The hardware complexity of digital filters is mainly dominated by the coefficient multipliers. Implementing fixed-point coefficient multiplication as a network of adders, subtractors, and shifters, yields lower power consumption. In such filters the number of adders (and subtractors) determines the implementation cost. The reason is that shifts are implemented as hard-wired inter-block connections and are considered “free”. In transposed implementation of an FIR filter, each input is multiplied by several coefficients. Considering all the coefficients as a multiplier block and omitting the redundancies by sharing the common fundamentals among different coefficients, yields great reduction in the number of arithmetic operations. This paper presents a graph based algorithm to reduce the computational complexity of multiple constant multiplications. Simulation results show that using the proposed method results good improvement in adder cost of multiplier blocks.

【 授权许可】

Unknown