A fast lock-in all-digital phase-locked loop in 40-nm CMOS technology

IEICE Electronics Express

Ching-Che Chung¹  Chi-Kuang Lo¹ 

[1] Department of Computer Science & Information Engineering, National Chung-Cheng University

关键词: all-digital phase-locked loop;    fast lock-in;    low power;   

DOI  :  10.1587/elex.13.20160749

学科分类：电子、光学、磁材料

来源: Denshi Jouhou Tsuushin Gakkai

【 摘 要 】

References(21)A system-on-a-chip (SoC) requires several phase-locked loops (PLLs) for providing different clock frequencies to different modules. Usually, analog PLLs cannot be stopped due to their long setting time. Hence, these PLLs dominate the system’s standby power consumption. In this paper, a fast lock-in all-digital PLL (ADPLL) that can achieve lock-in within 4.5 clock cycles is proposed to ensure that it can be switched off in the low power mode. The output frequency of the proposed ADPLL ranges from 125 MHz to 1.47 GHz, and the power consumption is 0.98 mW (at 0.9 V, 1.47 GHz).

【 授权许可】

Unknown