Efficient Realization of S-Box based reduced Residue of Prime Numbers using Virtex-5 and Virtex-6 FPGAs | Science Publications

American Journal of Applied Sciences

Mohammed H. Al Mijalli¹ 

关键词: Advanced Encryption Standard (AES);    Field Programmable Gate Array (FPGA);    Galois Field GF (28);    reduced residue of prime number;    Virtex-5;    Virtex-6;    VHDL;   

DOI  :  10.3844/ajassp.2011.754.757

学科分类：自然科学（综合）

来源: Science Publications

【 摘 要 】

Problem statement: The S-Box transformation is a computationally intensive and important operation of the Advanced Encryption Standard (AES). Approach: This study presents the comparative study between reduced Residue of Prime Numbers and Galois Filed GF (2⁸) based SBoxes using Virtex-5 and Virtex-6 FPGA devices. The implementation of S-Boxes is done using Very High speed integrated circuit Hardware Description Language (VHDL). Results: The results obtained from Virtex-6 FPGA show that the proposed method runs at a clock frequency of 0.785ns, which is three times faster than S-Box based on Galois Filed GF (2⁸). Conclusion: The reduced version of the S-Box based on prime number shows promising results as compared to Galois Field GF (2⁸) based SBox, which could be used in AES to increase its complexity and add more confusion.

【 授权许可】

Unknown