Multi-Threshold Dual-Spacer Dual-Rail Delay-Insensitive Logic (MTD3L): A Low Overhead Secure IC Design Methodology

Journal of Low Power Electronics and Applications

Michael Linder¹  Jia Di¹ 

[1] Department of Computer Science and Computer Engineering, University of Arkansas; Fayetteville, AR 72701, USA; E-Mails:

关键词: secure hardware;    side-channel;    asynchronous;    Advanced Encryption Standard (AES);   

DOI  :  10.3390/jlpea3040300

来源: mdpi

【 摘 要 】

As portable devices become more ubiquitous, data security in these devices is becoming increasingly important. Traditional circuit design techniques leave otherwise secure systems vulnerable due to the characteristics of the hardware implementation, rather than weaknesses in the security algorithms. These characteristics, called side-channels, are exploitable because they can be measured and correlated with processed data, potentially giving an attacker insight into the device’s secret data. Alternative design techniques such as dual-rail asynchronous designs are capable of minimizing these potential side-channels by decoupling them from the data being processed. However, these techniques are either expensive to implement compared to standard designs or leave exploitable imbalances in the dual-rail implementation itself. Multi-Threshold Dual-Spacer Dual-Rail Delay-Insensitive Logic (MTD³L) offers security by balancing side-channels both in general and between the dual-rail signals themselves, as well as reduction in circuit overhead compared to previous secure design techniques. Results show that the Advanced Encryption Standard (AES) cores designed using MTD³L exhibit similar security to previous secure techniques with substantially less area and energy overhead.

【 授权许可】

CC BY   
© 2013 by the authors; licensee MDPI, Basel, Switzerland.