Low Power Modulo 2n+1 Adder Based on Carry Save Diminished-One Number System | Science Publications

American Journal of Applied Sciences

Omid Kavehei¹  Somayeh Timarchi¹  Keivan Navi¹ 

关键词: Modulo 2n+1 addition;    carry save diminished-one number system;    parallel-prefix adders;    residue number system;    computer arithmetic;    VLSI circuits;   

DOI  :  10.3844/ajassp.2008.312.319

学科分类：自然科学（综合）

来源: Science Publications

【 摘 要 】

Modulo 2ⁿ+1 adders find great applicability in several applications including RNS implementations. This paper presents a new number system called Carry Save Diminished-one for modulo 2ⁿ+1 addition and a novel addition algorithm for its operands. In this paper, we also present a novel architectures for designing modulo 2ⁿ+1 adders, based on parallel-prefix carry computation units. CMOS implementations reveal the superiority of the resulting adders against previously reported solutions in terms of implementation area and delay.

【 授权许可】

Unknown