Reliable detection of CMOS stuck-open faults due to variable internal delays

IEICE Electronics Express

Afzel Noore¹ 

[1] Lane Department of Computer Science and Electrical Engineering West Virginia University

关键词: stuck-open faults;    design-for-testability;    CMOS circuits;   

DOI  :  10.1587/elex.2.292

学科分类：电子、光学、磁材料

来源: Denshi Jouhou Tsuushin Gakkai

【 摘 要 】

References(7)Cited-By(1)Testable designs for detecting single stuck-open faults in CMOS circuits have been proposed so that the tests remain valid even in the presence of unequal delays in the circuit. Existing approaches require the CMOS gate to be internally modified and are thus suitable for future chip designs. This paper proposes two versatile designs that can be adapted for both existing chips and new chip designs. A 3-sequence test set and a 2-sequence test set are derived for the proposed designs to reliably detect stuck-open faults.

【 授权许可】

Unknown