Selective scan slice repetition for simultaneous reduction of test power consumption and test data volume

IEICE Electronics Express

Sungho Kang¹  Yongjoon Kim¹  Jaeseok Park¹ 

[1] Department of Electrical and Electronic Engineering, Yonsei University

关键词: design-for-testability;    low-power testing;    scan testing;    test data compression;   

DOI  :  10.1587/elex.6.1432

学科分类：电子、光学、磁材料

来源: Denshi Jouhou Tsuushin Gakkai

【 摘 要 】

References(4)In this paper, we present a selective scan slice encoding technique for power-aware test data compression. The proposed scheme dramatically reduces test data volume via scan slice repetition, and generates an adjacent-filled test pattern known as the favorable low-power pattern mapping method. Experiments were performed on the large ITC'99 benchmark circuits, and results show the effectiveness of the proposed method.

【 授权许可】

Unknown