Floating-point operation based reconfigurable architecture for radar processing

IEICE Electronics Express

Baoning Zhang¹  Feng Han¹  Fan Feng¹  Guoqiang He²  Kun Wang¹  Li Li¹ 

[1] School of Electronic Science and Engineering, Nanjing University;Nanjing Research Institute of Electronics Technology

关键词: coarse-grained reconfigurable architecture;    floating-point unit;    radar signal processing;   

DOI  :  10.1587/elex.13.20160893

学科分类：电子、光学、磁材料

来源: Denshi Jouhou Tsuushin Gakkai

【 摘 要 】

References(15)To meet the increasing demand of large bandwidth and high throughput in modern radar system, we proposed a reconfigurable application specified processor (RASP) according to the feature of radar digital signal processing applications. RASP is a reconfigurable coprocessor based on hierarchical floating-point operation elements that is capable of executing a set of fundamental subalgorithms, take these subalgorithms as the minimal task node can improve the computational efficiency tremendously. The experimental results show that the processor performance exceeds TI state-of-the-art DSP by 1.05× to 3.22×. Our reconfigurable processor can be integrated into customizable radar systems, it was fabricated with TMSC 40 nm CMOS process and has an area of 19.2 mm2.

【 授权许可】

Unknown