Efficient implementation of LMS adaptive filter-based FECG extraction on an FPGA

Healthcare Technology Letters

article

Bhavya Vasudeva¹  Puneesh Deora¹  Pradhan Mohan Pradhan¹  Sudeb Dasgupta¹ 

[1] Department of Electronics and Communication Engineering, Indian Institute of Technology Roorkee

关键词: electrocardiography;    least mean squares methods;    medical signal processing;    adaptive filters;    flip-flops;    field programmable gate arrays;    obstetrics;    series architecture;    existing FPGA implementations;    FECG extraction methods;    LMS adaptive filter-based FECG extraction;    FPGA implementation;    foetal heart rate monitoring system;    preprocessing unit;    foetal electrocardiogram extraction unit;    FHR detection unit;    arithmetic operations;    floating-point unit;    mean squares;    LMS-AF;    lower utilisation;    parallel architecture;    convergence time;    extracted FECG;    noninvasive FECG databases;   

DOI  :  10.1049/htl.2020.0016

学科分类：肠胃与肝脏病学

来源: Wiley

【 摘 要 】

In this Letter, the field programmable gate array (FPGA) implementation of a foetal heart rate (FHR) monitoring system is presented. The system comprises a preprocessing unit to remove various types of noise, followed by a foetal electrocardiogram (FECG) extraction unit and an FHR detection unit. To improve the precision and accuracy of the arithmetic operations, a floating-point unit is developed. A least mean squares algorithm-based adaptive filter (LMS-AF) is used for FECG extraction. Two different architectures, namely series and parallel, are proposed for the LMS-AF, with the series architecture targeting lower utilisation of hardware resources, and the parallel architecture enabling less convergence time and lower power consumption. The results show that it effectively detects the R peaks in the extracted FECG with a sensitivity of 95.74–100% and a specificity of 100%. The parallel architecture shows up to an 85.88% reduction in the convergence time for non-invasive FECG databases while the series architecture shows a 27.41% reduction in the number of flip flops used when compared with the existing FPGA implementations of various FECG extraction methods. It also shows an increase of 2–7.51% in accuracy when compared to previous works.

【 授权许可】

CC BY|CC BY-ND|CC BY-NC|CC BY-NC-ND