Area-efficient reed-solomon decoder for 10Gbps satellite communication

IEICE Electronics Express

Hengzhu Liu²  Xianqiang Yang¹  Botao Zhang² 

[1] China Academy of Space Technology (CAST);Computer School, National University of Defense Technology

关键词: Reed-Solomon decoder;    area-efficient;    pipeline-balancing;   

DOI  :  10.1587/elex.8.1001

学科分类：电子、光学、磁材料

来源: Denshi Jouhou Tsuushin Gakkai

【 摘 要 】

References(6)This paper propose an area-efficient pipeline-balancing Reed-Solomon decoder for 10Gbps satellite communication. The proposed RS (244,212) is based on TD-iBM Key Equation Solver architecture, and Fixed-Factor Syndrome Computation & Chien Search. The decoder is implemented and verified in FPGA, and can work at 178MHz in Virtex2P. Thus a 8-channel FPGA implementation can be used for 10Gbps satellite communication systems. Additionally, the decoder is also synthesized in Chartered 90nm CMOS technology, and compared with previous decoders. The results show the decoder is more area-efficient than previous decoders. Meanwhile, by using this CMOS technology, the decoder can be clocked at about 1350MHz, so a single-channel ASIC implementation can meet the requirement of 10Gbps satellite communication.

【 授权许可】

Unknown