Vedic division methodology for high-speed very large scale integration applications

The Journal of Engineering

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[1] Department of Computer Science and Engineering, National Institute of Technology, Shillong, Meghalaya 793 003, India;Department of Electronics and Communication Engineering, National Institute of Technology, Shillong, Meghalaya 793 003, India;Department of Electronics and Telecommunication Engineering, Bengal Engineering and Science University, Shibpur, Howrah 711 103, India;

关键词: very high speed integrated circuits;    SPICE;    CMOS logic circuits;    dividing circuits;    size 90 nm;    digit-recurrence architectures;    Newton-Raphson architectures;    Goldschmidt architectures;    CMOS technology;    complementary metal oxide semiconductor technology;    spice spectre;    stage reduction;    divider circuitry;    dynamic power consumption;    propagation delay;    Dhvajanka formula;    ancient Vedic mathematics;    transistor level implementation;    high-speed very large scale integration applications;    Vedic division methodology;   

DOI  :  10.1049/joe.2013.0213

来源: publisher

【 摘 要 】

Transistor level implementation of division methodology using ancient Vedic mathematics is reported in this Letter. The potentiality of the ‘Dhvajanka (on top of the flag)’ formula was adopted from Vedic mathematics to implement such type of divider for practical very large scale integration applications. The division methodology was implemented through half of the divisor bit instead of the actual divisor, subtraction and little multiplication. Propagation delay and dynamic power consumption of divider circuitry were minimised significantly by stage reduction through Vedic division methodology. The functionality of the division algorithm was checked and performance parameters like propagation delay and dynamic power consumption were calculated through spice spectre with 90 nm complementary metal oxide semiconductor technology. The propagation delay of the resulted (32 ÷ 16) bit divider circuitry was only ∼300 ns and consumed ∼32.5 mW power for a layout area of 17.39 mm2. Combination of Boolean arithmetic along with ancient Vedic mathematics, substantial amount of iterations were reduced resulted as ∼47, ∼38, 34% reduction in delay and ∼34, ∼21, ∼18% reduction in power were investigated compared with the mostly used (e.g. digit-recurrence, Newton–Raphson, Goldschmidt) architectures.

【 授权许可】

CC BY