An inter-FPGA communication bus with error detection and dynamic clock phase adjustment

Brazilian Computer Society. Journal

SHC Santana¹  AG Silva-Filho¹  LT Melo¹  ME Lima¹  VWC Medeiros²  MLM Marinho² 

[1] Center for Informatics, Federal University of Pernambuco, Recife, Brazil;Statistics and Informatics Department, Federal Rural University of Pernambuco, Recife, Brazil

关键词: LVDS;    FPGA;    CRC;    Communication inter-FPGAs;   

DOI  :  10.1186/s13173-015-0026-z

学科分类：农业科学（综合）

来源: Springer U K

【 授权许可】

CC BY