期刊论文详细信息
Brazilian Computer Society. Journal | |
An inter-FPGA communication bus with error detection and dynamic clock phase adjustment | |
SHC Santana1  AG Silva-Filho1  LT Melo1  ME Lima1  VWC Medeiros2  MLM Marinho2  | |
[1] Center for Informatics, Federal University of Pernambuco, Recife, Brazil;Statistics and Informatics Department, Federal Rural University of Pernambuco, Recife, Brazil | |
关键词: LVDS; FPGA; CRC; Communication inter-FPGAs; | |
DOI : 10.1186/s13173-015-0026-z | |
学科分类:农业科学(综合) | |
来源: Springer U K | |