A 6 Gbps/pin Low-Power Half-Duplex ActiveCross-Coupled LVDS Transceiver with Switched Termination

ETRI Journal

关键词: I/O;    DRAM;    transceiver;    half-duplex;    LVDS;   

Others  :  1185667
DOI  :  10.4218/etrij.08.0207.0235

【 摘 要 】

A novel linear switched termination active cross-coupled low-voltage differential signaling (LVDS) transceiver operating at 1.5 GHz clock frequency is presented. On the transmitter side, an active cross-coupled linear output driver and a switched termination scheme are applied to achieve high speed with low current. On the receiver side, a shared pre-amplifier scheme is employed to reduce power consumption. The proposed LVDS transceiver implemented in an 80 nm CMOS process is successfully demonstrated to provide a data rate of 6 Gbps/pin, an output data window of 147 ps peak-to-peak, and a data swing of 196 mV. The power consumption is measured to be 4.2 mW/pin at 1.2 V.

   

【 参考文献 】

• [1]V. Bratov et al., "Architecture and Implementation of a Low-Power LVDS Output Buffer for High-Speed Applications," IEEE Trans. Circuits Syst. I, Regular Papers, vol. 53, no. 10, Oct. 2006, pp. 2101-2108.
• [2]A. Boni et al., "LVDS I/O Interface for Gb/s-per-pin Operation in 0.35 μm CMOS," IEEE J. Solid-State Circuits, vol. 36, no. 4, Apr. 2001, pp. 706-711.
• [3]M. Chen et al., "Low-Voltage Low-Power LVDS Drivers," IEEE J. Solid-State Circuits, vol. 40, no. 2, Feb. 2005, pp. 472-479.