A 33 Gb/s combined adaptive CTLE and half-rate look-ahead DFE in 0.13 µm BiCMOS technology for serial link

IEICE Electronics Express

Yinhang Zhang¹  Qingsheng Hu² 

[1] Institute of RF-&OE-ICs, Southeast University

关键词: equalizer;    CTLE;    DFE;    adaptive;    middle-frequency compensation;    serial link;   

DOI  :  10.1587/elex.15.20170764

学科分类：电子、光学、磁材料

来源: Denshi Jouhou Tsuushin Gakkai

【 摘 要 】

A 33 Gbit/s equalizer chip fabricated in 0.13 µm BiCMOS technology is presented. The proposed equalizer prototype includes adaptive continue time linear equalizer (CTLE) with middle frequency compensation and adaptive half-rate look ahead decision feedback equalizer (DFE). The slope detection based CTLE employs a two-path amplifier to adjust the ratio of the high frequency and low frequency adaptively, and a middle frequency amplifier dedicated to provide an appropriate compensation in the intermediate frequency range. For the half-rate DFE, by using a look ahead structure and an analog LMS algorithm circuit, the performance is improved in speed and area. Measurement results show that the equalizer chip can compensate lossy channel with a loss of 26 dB at 20 GHz effectively and the data rate can be up to 33 Gb/s under 3.3 V power supply, the total power consumption is about 726 mW at 33 Gb/s data rate.

【 授权许可】

CC BY