A 400-MS/s 10-b 8 interleaved SAR ADC in 0.13 um CMOS

IEICE Electronics Express

Danyu Wu¹  Xinyu Liu¹  Xiaoge Zhu¹  Jin Wu¹  Lei Zhou² 

[1] Insititute of Microelectronics of Chinese Academy of Sciences;University of Chinese Academy of Sciences

关键词: analog-to-digital converter;    SAR;    time-interleaved;    offset calibration;    adjustable reference buffer;   

DOI  :  10.1587/elex.14.20170067

学科分类：电子、光学、磁材料

来源: Denshi Jouhou Tsuushin Gakkai

【 摘 要 】

This paper presents an 8-channel time-interleaved SAR ADC. A novel sampling structure is proposed to improve the input bandwidth which also avoids time-skew calibration. The comparator offset cancellation is achieved by body voltage adjustment using low-power charge pump. Each channel has its own on-chip reference buffer to stable reference voltage and correct gain mismatches. The prototype is fabricated in 1P6M 0.13 µm CMOS technology. At 400 MS/s, the ADC achieves an SNDR of 50.84 dB and 45.7 dB at 19.1 MHz and 451 MHz, respectively. It consumes 200 mW, resulting in FOM of 1.76 pJ/con-step.

【 授权许可】

CC BY