An energy-efficient SAR ADC using a single-phase clocked dynamic comparator with energy and speed enhanced technique

IEICE Electronics Express

Minglei Zhang¹  Xiaohua Fan² 

[1] Institute of Microelectronics of Chinese Academy of Sciences;University of Chinese Academy of Sciences

关键词: SAR ADCs;    asynchronous;    dynamic comparator;    latch-type comparator;    cross coupling;    single phase clock;   

DOI  :  10.1587/elex.14.20170219

学科分类：电子、光学、磁材料

来源: Denshi Jouhou Tsuushin Gakkai

【 摘 要 】

This paper presents an energy-efficient 500 kS/s 8-bit SAR ADC with a novel dynamic comparator. The proposed dynamic comparator employs a cross-coupling cascode based preamp and an inverter-based pseudo-latch. This approach achieves a 40% higher speed, a 24% lower power consumption, and a similar input-referred noise level, compared with a conventional double-tail dynamic comparator. Moreover, only one single phase clock is required for the proposed comparator. The prototype ADC was fabricated in a 0.5 µm CMOS process with an active area of 0.18 mm2. Operating under a 1.8 V supply with Nyquist frequency input signal, the ADC consumes 18.2 µW at 500 kS/s and achieves SNDR and SFDR of 47.5 dB and 63.2 dB, respectively. Walden FoM of 188 fJ/conv.-step is achieved.

【 授权许可】

CC BY