A 42fJ 8-bit 1.0-GS/s folding and interpolating ADC with 1GHz signal bandwidth

IEICE Electronics Express

Mingshuo Wang¹  Fan Ye¹  Junyan Ren¹  Wei Li¹ 

[1] State Key Laboratory of ASIC and System, Fudan University

关键词: analog-to-digital converter;    folding and interpolating;    averaging resistors;    interpolating resistors;    offset voltages;    dynamic comparator;   

DOI  :  10.1587/elex.11.20130986

学科分类：电子、光学、磁材料

来源: Denshi Jouhou Tsuushin Gakkai

【 摘 要 】

References(8)A 1.0GHz signal bandwidth 8-bit folding and interpolating analog-to-digital converter (ADC) is presented, whose Fom is only 42fJ/Conv-step. In this design, averaging resistors and interpolating resistors are shared, which can be save pr-amplifiers and active interpolators. Grouped T/H blocks are adopted to cancel the voltage buffer between the T/H block and the pre-amplifiers array. A new full-digital T/H switch is proposed to cancel the bootstrapped capacitor, which can save the area of chip grandly. A new linear and continues offset voltages of dynamic comparator calibration method is presented. This ADC implemented in 65nm CMOS technology achieves SNDR of 48.5dB and SFDR of 58.7dB for 479.5MHz input frequency at the rate of 1.0-GS/s. And the SNDR and SFDR maintain above 48dB and 55dB, respectively, up to 995.1MHz. The power consumption is only 17mW with a supply voltage of 1.2V.

【 授权许可】

Unknown