An improved phase digitization mechanism for fast-locking low-power all-digital PLLs

IEICE Electronics Express

Shu-shan Qiao¹  Lin-lin Xie¹  Yong Hei²  Yang Wang² 

[1] Institute of Microelectronics of Chinese Academy of Sciences;University of Chinese Academy of Sciences

关键词: ADPLL;    TDC;    fast locking;    low power;    phase digitization;   

DOI  :  10.1587/elex.14.20170911

学科分类：电子、光学、磁材料

来源: Denshi Jouhou Tsuushin Gakkai

【 摘 要 】

An improved phase digitization mechanism is designed to overcome limited lock-in range of low-power all-digital phase-locked loop (ADPLL) with phase prediction and edge snapshot circuit. The proposed mechanism including a dual-mode multiplexer-based time-to-digital converter (TDC) and accessional algorithm is verified in a modelled and simulated ADPLL. Results show that the ADPLL is able to lock in 7.8 µs, i.e., 187 cycles with a 24 MHz reference clock. The ADPLL also has strong recovery capability from sudden disturbance, for instance, it recovers in 8 µs with 0.38% disturbance.

【 授权许可】

CC BY