Design and Implementation of Fast Locking All-Digital Duty Cycle Corrector Circuit with Wide Range Input Frequency

Electronics

Shao-Ku Kao¹ 

[1] Department of Electrical Engineering and Green Technology Research Center, Chang Gung University, Tao-Yuan 330, Taiwan;

关键词: fast locking;    all-digital;    duty cycle corrector (DCC);    wide range correction;   

DOI  :  10.3390/electronics10010071

来源: DOAJ

【 摘 要 】

This paper presents a fast locking and wide range input frequency all-digital duty cycle corrector (ADDCC). The proposed ADDCC circuit comprises a pulse generator and a clock generator. The pulse generator is edge-triggered by an input signal to produce a 0 degree and 180 degree phase. The clock generator uses a 0 degree and 180 degree phase to produce the 50% duty cycle output signal. It corrects the duty cycle of the input signal in six clock cycles. The proposed ADDCC is implemented in a 0.35 µm CMOS process. The circuit can operate from 10 MHz to 100 MHz, and accommodates a wide range of input duty cycles ranging from 30% to 70%. The duty-cycle error of the output signal is less than ±1%.

【 授权许可】

Unknown